Electronic design automation

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Electronic design automation (EDA) is the category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. This is sometimes referred to as ECAD (electronic computer-aided design).

The term EDA is also used as an umbrella term for computer-aided engineering, computer-aided design and computer-aided manufacturing of electronics in the discipline of electrical engineering. This usage probably originates in the IEEE Design Automation Technical Committee.

EDA has rapidly increased in importance with the continuous scaling of semiconductor technology. (See: Moore's Law.) The largest segment of EDA users are chip designers at semiconductor companies, who design chips using EDA software. Other users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs.

Contents

Product areas (incomplete)

EDA is divided into many (sometimes overlapping) sub-areas. They mostly align with the path of manufacturing from design to mask generation. The following applies to chip/ASIC/FPGA construction but is very similar in character to the areas of printed circuit board design:

  • Design and Architecture: design the chip's schematics, output in Verilog, VHDL, SPICE and other formats.
  • Floorplanning: The preparation step of creating a basic die-map showing the expected locations for logic gates, power & ground planes, I/O pads, and hard macros. (This is analogous to a city-planner's activity in creating residential, commercial, and industrial zones within a city block.)
  • Logic synthesis: translation of a chip's abstract, logical RTL-description (often specified via a hardware description language, or "HDL", such as Verilog or VHDL) into a discrete netlist of logic-gate (boolean-logic) primitives.
  • Behavioral Synthesis, High Level Synthesis or Algorithmic Synthesis: This takes the level of abstraction higher and allows automation of the architecture exploration process. It involves the process of translating an abstract behavioral description of a design to synthesizeable RTL. The input specification is in languages like behavioral VHDL, algorithmic SystemC, C++ etc and the RTL description in VHDL/Verilog is produced as the result of synthesis.
  • Intellectual property blocks: provide pre-programmed design elements.
  • Simulation: simulate a circuit's operation so as to verify correctness and performance.
    • Transistor Simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
    • RTL Simulation – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, accurate at boolean-level.
    • Behavioral Simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
  • Formal verification: algorithmic-comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalency at the logical level.
  • Place and route, PAR: (for digital devices) tool-automated placement of logic-gates and other technology-mapped components of the synthesized gate-netlist, then subsequent wiring of the components' signal and power terminals.
  • Transistor layout: (for analog/mixed-signal devices), sometimes called polygon pushing – a prepared-schematic is converted into a layout-map showing all layers of the device.
  • Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.
    • Design rules checking, DRC – checks a number of rules regarding placement and connectivity required for manufacturing.
    • Layout versus schematic, LVS – checks if designed chip layout matches schematics from specification.
    • Parasitic device extraction, RCX – extracts parasitic resistors (PRE), and often capacitors (RCX), and sometimes inductors, inherent in the chip layout.
  • Mask data preparation, MDP: generation of actual lithography photomask used to physically manufacture the chip.
  • Manufacturing Test
    • design for test, DFT – adds logic-structures to a gate-netlist, to facilitate post-fabrication (die/wafer) defect testing.
    • automated test pattern generation, ATPG – generates pattern-data to systematically exercise as many logic-gates, and other components, as possible.

Largest companies

Company Location Market Value Logo
Cadence Design Systems San Jose, California $3.5 billion Image:CadenceDesignSystemsLogo.GIF
Synopsys Mountain View, California $2.5 billion Image:SynopsysLogo.GIF
Mentor Graphics Wilsonville, Oregon $1.0 billion Image:MentorGraphicsLogo.GIF
Magma Design Automation Inc Santa Clara, California $387 million Image:MagmaDALogo.gif

See also

External links

Open source EDA tools

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